Principle Engineer of Intel Corp will be Vanderbilt's Colloquium Speaker 3.4.10

Dr. Shubu Mukherjee from Intel will be our EECS colloquium speaker this Thursday. Those who are interested in meeting with Dr. Mukherjee should contact Aniruddha Gokhale at gokhale [at] The meeting will be at 9 am in FGH 257 on Thursday (March 4th).

Abstract below:

“Architectural Vulnerability Factor (or does a soft error matter)?”

Dr. Shubu Mukherjee
Intel Corporation

Thursday, March 4, 2010 at 3PM
Jacobs Believed in Me Auditorium, Room 134, Featheringill Hall

Abstract: With each technology generation, we experience an increased rate of cosmically induced soft errors in our chips. We are starting to see a dark side to Moore's Law in which the increased functionality we get with our exponentially increasing number of transistors is being countered with an exponentially increasing soft error rate. Increased effort and cost are required to cope with this issue. Design solutions for this problem are inherently expensive, and protecting all structures is often prohibitive for the commercial processor market.

A key aspect of estimating a processor's soft error rate is to compute the architectural vulnerability factor (AVF) of its constituent structures, such as a reorder buffer or writeback queue. A structure's (AVF) is the probability that a fault in that particular structure will result in an error in the final output of a program. A structure's error rate is the product of its raw error rate, as determined by process and circuit technology, and the AVF. Processor designers can use these AVF estimates to determine which structures need protection (e.g., structures with high AVF are likely to be protected). In this talk, I will describe the soft error problem and how AVF can be estimated to help processor designers choose the most cost-effective protection scheme.

Biography: Shubu Mukherjee is a Principal Engineer and Director of Intel's SPEARS Group (Simulation and Pathfinding of Efficient and Reliable Systems). The SPEARS Group is responsible for spearheading architectural change and innovation in the delivery of enterprise processors and chipsets by building and supporting simulation and analytical models of performance, power, and reliability. Dr. Mukherjee has taken five innovations in large-scale system monitoring, soft error tolerant microarchitectures, performance simulation, parallel simulation, and on-chip interconnect algorithms from conception to implementation.

In 2009, Dr. Mukherjee won the Maurice Wilkes award for outstanding contributions to computer architecture. This is the highest award given to a mid-career architect. Dr. Mukherjee is also a Fellow of IEEE and a Distinguished Member of ACM. He was the General Chair of 2004 ASPLOS and will be the Program Chair for 2011 HPCA. He wrote the seminal book, "Architecture Design for Soft Errors," holds 25 patents, has 23 patents pending, and has written over 50 technical papers in top architecture conferences and journals. Prior to joining Intel, Dr. Mukherjee worked for Digital Equipment Corporation and Compaq Computer Corporation. His current interests include innovation confluencing, computer architecture, and fault tolerance.