From System Modeling to Formal Verification

TitleFrom System Modeling to Formal Verification
Publication TypeConference Proceedings
Year of Conference2015
AuthorsChhokra, A., S. Abdelwahed, A. Dubey, S. Neema, and G. Karsai
Refereed DesignationDoes Not Apply
Conference NameThe 2015 Electronic System Level Synthesis Conference
Series TitleESLsyn2015
Date Published07/01/2015
Conference LocationSan Francisco
ISBN Number979-10-92279-12-2

Due to increasing design complexity, modern systems are modeled at a high level of abstraction. SystemC is widely accepted as a system level language for modeling complex embedded systems. Verification of these SystemC designs nullifies the chances of error propagation down to the hardware. Due to lack of formal semantics of SystemC, the verification of such designs is done mostly in an unsystematic manner. This paper provides a new modeling environment that enables the designer to simulate and formally verify the designs by generating SystemC code. The generated SystemC code is automatically translated to timed automata for formal analysis.

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